1. Field
Aspects of the present disclosure relate generally to synchronizers, and more particularly, to resolving a metastable state in a synchronizer.
2. Background
Two different blocks in a device may operate at different clock frequencies. As a result, when one of the blocks (a sender block) sends a data signal to the other block (a receiver block), the data signal is asynchronous with respect to the receiver block. In this regard, the receiver block may include a synchronizer to synchronize the incoming data signal with a clock of the receiver block. The synchronizer may do this by capturing data values of the data signal on the rising and/or falling edges of the receiver clock.
In order for the synchronizer to properly capture a data value of the data signal, the data signal should be stable for a time period before a rising or falling edge of the clock (setup time) and for a time period after the rising or falling edge of the clock (hold time). However, since the data signal is asynchronous with respect to the receiver block, the data signal may transition between values during the setup time and/or the hold time, resulting in a setup-time violation and/or a hold-time violation. When this occurs, the synchronizer may go into a metastable state that is neither a logic one nor a logic zero. If left unresolved, the metastable state can cause the receiver block to malfunction.